Increasing performance with multiply-add units and wide buses

A balanced increase of memory bandwidth and computational performance is one of the current trends towards high performance microprocessors. This improvement can be attained either by replicating resources such as buses and functional units or by making them more complex. For example, some microprocessors, as the IBM’s POWER2 double the width of the buses between the register file and the first-level data cache in order to get similar results as by doubling the number of buses, but at a lower cost. In a similar way, some microprocessors have multiply-add fused functional units to increase the computation capability, as IBM’s POWER2 and RS6000 processors. In this paper we evaluate the performance and the effects on register pressure of these alternatives. The performance benefits have been evaluated using 1180 kernel loops of the Perfect Club benchmarks, which account for 78% of the total execution time. The results show that both techniques (widening buses and using multiply-add fused functional units) are complementary cost-effective solutions to increase the processor efficiency in numerical applications.